1. Field of the Invention
The present invention relates to an integrated circuit semiconductor device having an improved wiring structure, and more particularly, to a semiconductor memory device such as non volatile semiconductor memory device having floating and control gate electrodes.
2. Description of Related Art
A MOS type semiconductor memory device has heretofore been constructed so that contacts are provided on the memory cell drain diffusion layers to make connections to respective aluminium wirings used as bit lines in order to effect the programming and the reading operation. With the above-mentioned conventional MOS type semiconductor memory device, however, a contact must be formed on the drain of each of the memory cells causing a serious hindrance to a further reduction of the cell area of a unit bit which is the modern tendency toward increasing the capacity of a memory. Moreover, a non volatile semiconductor memory device uses double polycrystalline silicon layers; the lower layer constituting floating gate electrodes and the upper layer constituting word lines including control gate electrodes. Therefore, when an attempt is made to decrease the distance among the word lines in order to decrease the cell areas, the contact sandwiched between the two words lines is tapered very steeply, and becomes apt to be broken down.
Furthermore, when the interlayer insulating film between bit lines and word lines including control gate electrodes and forming the contact openings therein becomes thin due to a variance in the etching at the time of forming the contact openings, the polycrystalline silicon layer forming word lines and the aluminum bit lines are capacitively coupled to each other; i.e., they cannot be independently selected and the data cannot be read out. In extreme cases, a hole is unfavorably formed in the interlayer insulating film causing the word lines and the bit lines to be short-circuited. Furthermore, a drain diffusion layer is required having an area which is large enough to provide a drain contact, which is detrimental to reducing the cell area.
To eliminate these disadvantages, which are caused by the contact structure, a new non volatile semiconductor memory device is proposed by J. Esquivel et al. entitled "HIGH DENSITY CONTACTLESS, SELF ALIGNED EPROM CELL ARRAY TECHNOLOGY" in IEDM 86, pp. 592 to 595. In the new device, the drain diffusion layers are formed in the major surface of the semiconductor substrate and extend in one direction as the bits lines which are in parallel with each other. Also, the source diffusion layers are formed in the major surface of the substrate and extend in the same one direction. A pair of source diffusion layers are thus formed at both sides of one drain diffusion layer. The device is not necessary to provide a drain contact; therefore, the disadvantages mentioned above can be eliminated. However, both bit and voltage diffusion layers are formed in the same major surface of the substrate; therefore, a degree of a high integration density is limited in some extent. Further, both bit and voltage diffusion layers extend in the same direction. Therefore, a conventional decoder circuit to select one bit cell can not be employed, and a new and complicated one is necessary.